|| Kean Electronics
TP-Link WR703N Expander - Open Source Hardware
Developed in conjunction with the Sydney Hackerspace
Robots and Dinosaurs Inc – June 2012
(featured on Hack A Day 24th June 2012)
This project is a small USB Hub & FTDI dual serial/GPIO/JTAG adapter.
It was designed to match the form factor of the TP-LINK WR703N router, but can be used with almost any USB host.
If you haven't used the WR703N - it is a great little OpenWRT box, made even better with the I/O expansion from this board.
How To Get One
As of June 2012, we now have some commercially made PCB's of the V1 design. Kean is populating them with the SMD parts when he has time.>
They will be available at cost ($20) to R+D members, or same + shipping to other Aussie hackerspace members. (WR703N and enclosure not included)
I get weekly enquiries about these PCB's, but I don't have the time or funds to do another production run.
If you'd like to see these boards available for sale worldwide, please vote for them at the
Seeed Studios Wish page
- The upstream USB connection is intended to come via a 4 pin header plugged into the WR703N PCB below (existing USB connector removed).
- You can also populate a mini-B connector for connection to any upstream USB host via a cable.
- You can populate up to 3 USB A female connectors, or use 0.1" headers/connectors to mount USB connectors elsewhere.
- USB1 and USB2 are intended to be standard right angle connectors, but will also take vertical style.
- USB2 is recessed - partly to make the PCB able to be mounted very low on top of the WR703N PCB, but it also makes it suitable for very small USB drives (Sandisk Cruzer Fit).
- USB3 can be a right angle or more usually a vertical connector. Or left off completely.
- If a right angle connector is used for USB3, you can't easily use PORTB (and you should probably put some insulating tape over the PORTB pads).
- The PORTA and PORTB headers are similar to the common SparkFun FTDI connector, although they include RTS instead of DTR.
- The GPIO connector is intended to be a standard 2x5 box header.
- See the schematic for pin outs of the GPIO and serial ports. Due to space restrictions, the extra 8 GPIO's from PORTB are not routed out.
- JMP1: hub reports as "self powered" (standard - near USB hub chip) or "bus powered" (alternate - near JMP1 label)
- JMP2: 5V power from upstream USB (standard - near C11) or external 5V IN (alternate - near left edge)
- JMP3: port A VCC set to 3.3V (standard - near JMP3 label) or 5V (alternate - near bottom edge)
- JMP4: port B VCC set to 3.3V (standard - near JMP4 label) or 5V (alternate - near bottom edge)
Theory of Operation
- It is pretty much just based on reference designs for GL850G USB Hub and FTDI FT2232L.
- The only unusual bit is the tiny logic schmitt trigger inverter and flip-flop to create a 5V 6MHz clock for the FT2232L from the 12MHz clock of the GL850G.
- There is a fuse on the 5V rail to avoid damaging upstream equipment.
- The 3.3V supply comes from the GL850G USB hub chip, and is limited in output (200mA max total).
- Be careful not to draw too much power from either 5V or 3.3V supplies. Note that I've seen USB 5V rails drop to as low as 4.4V.
- There are some footprints for optional components, like Y1B+R7 (for an SMD ceramic resonator), or F1A (for a 400mA polyswitch).
Circuit Diagram & Files (for V1)
This project is licensed under the
Creative Commons Attribution ShareAlike license
© 2009-2012 Kean Electronics, A.B.N. 30 975 829 467
Last updated: 29th April 2013